The present invention relates to a semiconductor memory device, particularly to a static RAM having 4-transistor bistable type memory cells.
A typical circuit configuration of a 4-transistor bistable type static memory cell of a read/write memory or random access memory (RAM) is as shown in FIG. 1. In FIG. 1, cross-coupled MOS transistors Q1 and Q2 and drain load resistors R1 and R2 form a bistable flip-flop (FF). One node N1 of this FF is coupled via a transfer gate MOS transistor Q3 to a data line DL. The other node N2 of FF is coupled via a transfer gate MOS transistor Q4 to another data line DL. The gate of each of transistors Q3 and Q4 is connected to a word line WL.
FIG. 2 shows a conventional semiconductor configuration embodying the circuit of FIG. 1. In FIG. 2, the drain area D1 of transistor Q1 is separated by a Vss line pattern from the drain area D2 of transistor Q2, and the N.sup.+ areas of nodes N1 and N2 connected to D1 and D2 are relatively large. Thus, the drains D1 and D2 of the FF are liable to absorb minority carriers produced around the N.sup.+ areas of nodes N1 and N2. Such minority carriers could be generated from the neighboring circuit element in the same semiconductor substrate and/or generated by .alpha. irradiation applied to the semiconductor. Further, a configuration such as showing FIG. 2 would cause an overly large absorption of carriers into the drain areas D1 and D2, resulting in a large soft error rate.
This is the first disadvantage of the prior art configuration of FIG. 2.
Here, the erroneous destruction of stored data caused by natural radiant rays (.alpha. particles) is called a "soft error". A soft error may be defined as random single-bit error of a memory device.
According to the configuration of FIG. 2, the figure of a gate pattern on the gate region (channel) of each of transistors Q1 and Q2 is curved. From this, as seen from FIGS. 3A-3D, if an erroneous deviation of the gate pattern mask occurs during the manufacturing of a semiconductor memory, the overlapping area between a gate electrode pattern GP and a gate region GR of semiconductor will vary. FIG. 3A shows an example of a normal or target location of the gate pattern GP with reference to the gate region GR which includes the channel region of a MOS transistor electrode. FIG. 3B shows a case where the pattern mask of gate electrode pattern GP deviates toward the right side. FIG. 3C shows a case where the pattern mask of GP deviates toward the under side. FIG. 3D shows a case where the pattern mask of GP deviates toward the right under side. In any of FIGS. 3B-3D, the overlapping area between GP and GR (hatched portion) differs from the normal one (FIG. 3A). Thus, when the position of the gate pattern mask of Q1 and Q2 deviates from the target position during the manufacture of the memory, a variation of the conductance gm of Q1, Q2 and a variation of the node capacitance CN of N1, N2 become large. Such large variations of gm and CN will cause degradation of the bistable stability of the FF. When the bistable stability is degraded, the noise margin of the FF is lowered.
This is the second disadvantage of the configuration of FIG. 2.
Here, a good bistable stability for flip-flop provides the following features:
(i) a potential difference between the high potential node (data "1") and the low potential node (data "0") before inverting the potential state of the flip-flop is sufficiently large, and
(ii) the potential change curve of one node (N1) of the flip-flop is symmetrical with that of the other node (N2) with respect to the level inversion point of the flip-flop.
Further, according to FIG. 2, the extending direction of a pattern of resistor R1 differs from that of resistor R2. FIG. 4A shows a simplified example of a normal or target location of a resistor pattern RP for resistors R1 and R2 with reference to the regions of Vcc, D1 and D2 (R1=R2). FIG. 4B shows a case where the pattern mask of resistor pattern RP deviates toward the right side, and FIG. 4C shows a case where the pattern mask of RP deviates toward the under side. In the case shown in FIG. 4B, the resistance value of R1 is increased to R1B, while the resistance value of R2 does not vary (R1B&gt;R2). In the case shown in FIG. 4C, the resistance value of R2 is increased to R2C, while the resistance value of R1 does not vary (R1&lt;R2C). From this, if the resistor pattern mask for R1 and R2 deviates from the target position, the effective resistance value of R1 becomes different from that of R2. This also degrades the bistable stability. Therefore, when the potential of node N1 of FIG. 2 becomes close to the potential of node N2 due to an injection of carriers, an errorneous data change of the FF, or the destruction of the stored contents of the memory cell, is likely to occur.
This is the third disadvantage of the configuration of FIG. 2.
In order to satisfactorily improve the bistable stability, the gm of transistor Q1 should be as close the gm of transistor Q2 as possible, the CN of node N1 should be as close the CN of node N2 as possible and the resistance R1 should be as close the resistance R2 as possible.
The above disadvantages--large soft error rate and degradation of bistable stability--become more conspicuous as the integration density of the semiconductor device increases, and the channel width of transistors Q1 and Q2 of each memory cell becomes narrow.